Curriculum Vitae

A compact PDF version of the CV can be found here (Last update: August 2026).

Education

• Ph.D. in Electrical and Computer Engineering, Purdue University, West Lafayette, expected May 2029
  • Advisor: Prof. Kaushik Roy
  • GPA: 4/4
  • Research: Advanced node memory design; mixed-signal circuit design for compute-in-memory; circuit design with emerging embedded memory technologies; hardware-algorithm co-design for efficient computing
• B.Tech. in Electrical Engineering, Indian Institute of Technology Delhi, May 2024
  • GPA: 9.15/10
  • Department Rank: 4/192
  • Best Bachelor Thesis in Electrical Engineering (advisor: Prof: Debanjan Bhowmik)

Research Experience

• Tapeout of a 22nm MRAM-Based Compute-in-Memory Accelerator
  Collaboration with imec, Belgium (August 2025 - May 2026)
  • Part of a four-chip magnetoresistive RAM (MRAM) compute-in-memory prototype tapeout for accelerating DNN matrix-vector multiplications in GlobalFoundries (GF) 22nm.
  • Designed and laid out one of the four chips, including MRAM arrays, sensing peripherals, and calibration circuits for correcting analog non-idealities.
  • Built the shared tapeout infrastructure used across all four chips, including the GF 22nm RTL-to-GDSII flow for digital logic and a custom I/O pad ring.
• Ternary Gain-cell Compute-in-Memory Macro in 22nm (January 2026 - May 2026)
  • Developed a high-density gain-cell analog compute-in-memory macro with ternary bit-cell storage for highly quantized matrix-vector multiplications, reducing ADC conversion overhead for DNN acceleration.
  • Designed and laid out a 64×64 all-NMOS 3T gain-cell array with compute peripherals and self-calibration circuitry to mitigate transistor-mismatch-induced non-idealities.
  • Achieved 2.6× higher density than 8T-SRAM for equivalent compute-in-memory functionality.
• In-Memory Probabilistic Computing for Combinatorial Optimization
  Collaboration with imec, Belgium (April 2025 - July 2025)
  • Developed a compute-in-memory architecture for accelerating NP-hard large-scale routing problems.
  • Designed 8T-SRAM arrays and sense amplifiers integrating spin-based devices for probabilistic computing.
  • Developed control logic to execute in-memory optimization cycles for large-scale routing problems.
  • Cycle-accurate evaluations of the ASIC implementation project 7 and 14 orders-of-magnitude improvement in time-to-solution and energy efficiency, respectively, compared with a CPU, with <15% quality loss.

Current Research

• In-Memory Boolean Operations in 2nm Nanosheet FET Technology
  Collaboration with imec, Belgium (August 2026 - Present)
  • Developing 8T-SRAM arrays and supporting digital logic in imec 2nm nanosheet FET technology for in-memory Boolean operations, targeting accelerated k-nearest-neighbor search in graph-based combinatorial optimization.

Technical Skills

• EDA Tools: Cadence Virtuoso, Genus, Innovus
• HDLs & Programming: Verilog, SystemVerilog, Python, C
• Circuit & VLSI Design: Custom circuit design and layout, synthesis, PNR, STA, RTL-to-GDSII flow, tapeout

Relevant Coursework

• MOS VLSI Design, Advanced VLSI Design, Solid State Devices, AI Hardware, CMOS Analog IC Design

Work and Research Positions

• August 2024 - Present: Graduate Research Assistant, Purdue University
  • Supervisor: Prof. Kaushik Roy
• December 2021 - June 2024: Research Assistant, NAITS Group
  • IIT Delhi / IIT Bombay
  • Supervisor: Prof. Debanjan Bhowmik
• July 2023 - December 2023: Research Assistant, CSNDL Lab
  • IIT Delhi
  • Supervisor: Prof. Saurabh Gandhi

• Summer 2023: Data Scientist, Ripik AI

• Winter 2022: Hardware Engineer Intern, Aeronautical Development Establishment, DRDO

• Summer 2022: Research Assistant, CAN Lab (remote)
  • The University of Hong Kong
  • Supervisor: Prof. Can Li

Publications

LIMO: Low-power in-memory-annealer and matrix-multiplication primitive for edge computing

Amod Holla, Sumedh Chatterjee, Sutanu Sen, Anushka Mukherjee, Fernando García-Redondo, Dwaipayan Biswas, Francesca Iacopi, and Kaushik Roy
npj Unconventional Computing 3, Article 10, 2026
DOI: 10.1038/s44335-026-00054-8

ROSETTA: ROM-Overlaid STT-MRAM for Efficient MVM and Softmax Operations Toward Accelerating Transformer Inference

Amod Holla, Mainakh Mukherjee, Anushka Mukherjee, and Kaushik Roy
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 16(2), 441-454, 2026
DOI: 10.1109/JETCAS.2026.3665635

TAXI: Traveling Salesman Problem Accelerator with X-Bar-Based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering

Sangmin Yoo, Amod Holla, Sourav Sanyal, Dong Eun Kim, Francesca Iacopi, Dwaipayan Biswas, James Myers, and Kaushik Roy
62nd ACM/IEEE Design Automation Conference (DAC), Article 60, pp. 1-7, 2025
DOI: 10.1109/DAC63849.2025.11132522

Spintronics-Based Neuromorphic and Ising Computing

Debanjan Bhowmik, Ram Singh Yadav, Neha Garg, Amod Holla, Pranaba K Muduli
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India 2024 pp. 1-3
DOI: 10.1109/EDTM58488.2024.10511458

Impact of edge defects on the synaptic characteristic of a ferromagnetic domain-wall device and on on-chip learning

Ram Singh Yadav, Aniket Sadashiva, Amod Holla, Pranaba Kishor Muduli and Debanjan Bhowmik
Neuromorphic Computing and Engineering 2023 3 034006
DOI: 10.1088/2634-4386/acf0e4

Demonstration of synaptic behavior in a heavy-metal-ferromagnetic-metal-oxide-heterostructure-based spintronic device for on-chip learning in crossbar-array-based neural networks

Ram S. Yadav, Pankhuri Gupta, Amod Holla, Kacho Imtiyaz Ali Khan, Pranaba K. Muduli, and Debanjan Bhowmik
ACS Applied Electronic Materials 2023 5(1), 484-497
DOI: 10.1021/acsaelm.2c01488

Teaching

Teaching Assistant, Introduction to Electrical Engineering (Theory and Lab)

Additional Interests

• Hiking, Traveling, Gardening, Lifting, Cooking, Aviation