ROSETTA: ROM-Overlaid STT-MRAM for Efficient MVM and Softmax Operations Toward Accelerating Transformer Inference

Abstract: Compute-in-memory architectures can reduce the data-movement bottleneck of deep-learning accelerators by performing matrix-vector multiplications directly within memory arrays. Transformer inference, however, also requires nonlinear operations such as softmax, while conventional STT-MRAM compute-in-memory arrays face limitations from low device resistance, parasitic effects, and restricted row-level parallelism. ROSETTA introduces a 3T-2R STT-MRAM compute-in-memory bit-cell using series-resistance sensing and time-to-digital conversion for energy-efficient matrix-vector multiplication. An additional word line overlays ROM functionality onto the array, allowing lookup tables used for softmax to be stored without increasing bit-cell area. A palindromic input and weight encoding scheme mitigates data-dependent nonlinearity and enables substantially higher row parallelism. Compared with an equivalent ROM-overlaid 8T-SRAM implementation, the proposed macro reduces both area and MVM energy while maintaining comparable latency and accuracy.

Recommended citation: Amod Holla, Mainakh Mukherjee, Anushka Mukherjee, and Kaushik Roy
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 16(2), 441-454, 2026
DOI: 10.1109/JETCAS.2026.3665635
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